The present invention relates to a heatsink attachment module and, more particularly, to a thermal interface material (TIM) gap control for a direct heatsink attachment module.
In the packaging of semiconductor chips, an organic substrate is typically used. The organic substrate fans out the fine pitch, typically 0.15 to 0.2 mm, controlled collapse chip connection (C4) solder bumps on the silicon die to larger pitch, typically 1.0 to 1.2 mm, ball grid array (BGA) or land grid array (LGA) connections. With a BGA, the chip package is attached to a printed circuit board by the reflow of the solder balls to form a permanent connection. An LGA type interposer provides a connection where the chip package can be readily removed and replaced on the printed circuit board (PCB).
In general, with an organic packaging substrate, a lid formed from a thermally conductive material, such as copper, is attached to the chip and the organic substrate to protect the chip during handling and to add mechanical strength to the organic substrate. A thermal interface material (TIM) material is dispensed between the back surface of the chip and the lid to provide a thermal path for heat dissipation. If required, a heat sink is then attached using a second TIM layer to the outside surface of the lid. The chip is mounted face, or device side, down on the packaging substrate. When used with an LGA interposer, where a compressive load through the chip, the LGA and the PCB is required for electrical contact, the load is applied to the package lid either in the center above the chip or at two or more points on the perimeter. Due to the differences in thermal expansion coefficient between the organic substrate, the chip and the lid, unique assembly processes for the above-described operations may be required.
For multichip modules (MCMs) on ceramic substrates, to improve the thermal performance, it is often desirable to customize the lid so that a thin uniform TIM layer can be provided on multiple chips, independent of chip tilt or height variations. A previous method to achieve this has involved customizing the location of cylindrical holding elements by placing shims on the chips and reflowing solder to secure the holding elements to the inner surface and edges of the openings. When a lid is used, the cooling path for the chip contains two TIM layers, one on the chip side of the lid and a second between the lid and the heat sink. For some applications, this can be an unacceptable limitation.
For high performance computing, there has been significant development work on various types of chip stacks as it is becoming increasingly difficult to further improve device performance by scaling down the dimensions. In some chip stacks, the chips are thinned down to enable the fabrication of fine pitch thru silicon vias (TSV), which can reduce the mechanical strength of the chips, so it may be desirable to not provide the actuation load for an LGA through the chip stack, especially as the size of the substrate, and hence the required load, increases. For applications with a high power density, or which require a low junction operating temperature, a packaging solution where the heat sink can be directly attached to the back surface of the chip or chip stack may be required. The use of only a single TIM layer between the chip or chip stack and the heat sink results in improved thermal performance compared to a lidded chip package where two TIM layers are required. This is typically referred to as a lidless or direct heat sink attach package. For high performance systems, it is generally desirable to use LGA chip packages instead of BGA chip packages so that the chip can be replaced if necessary. As the chip complexity increases and the power and input/output (I/O) requirements grow, the size of the package generally increases to provide a greater number of LGA contacts. For a lidless package where the LGA actuation load is provided through the chip, the substrate, or the combination of the substrate and top surface stiffener, there is a need to provide enough mechanical rigidity to distribute the load with sufficient uniformity across the LGA interposer to form electrical contact for all the pads. For organic substrates, this may limit the allowable substrate size and for ceramic substrates this may increase the required thickness. When the LGA actuation load is provided to the substrate, a load frame (or stiffener) with an opening for the chip, may be attached to the substrate and the combined structure needs to provide adequate mechanical stiffness to actuate the LGA uniformly. Such a load frame, or stiffener, would be attached to the substrate.